Chiplets hold the potential to deliver the same power, performance, and area benefits as an SoC, but with many more features and options that are possible on a reticle-constrained die. If chiplets live up to the hype, they will deliver what is essentially mass customization, democratizing and speeding the delivery of complex chips across a broad array of markets. Today, the focus has been on die-to-die interfaces, but there is much more work ahead. Andy Heinig, head of efficient electronics in Fraunhofer IIS’ Engineering of Adaptive Systems Division, talks with Semiconductor Engineering about power delivery and thermal dissipation in chiplets, where these limited-function devices are likely to show up first, and why issues like uneven aging, stress, and warpage will create new challenges for design engineers.